MSP430.ob07 2.6 KB

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  1. (*
  2. BSD 2-Clause License
  3. Copyright (c) 2019-2021, Anton Krotov
  4. All rights reserved.
  5. *)
  6. MODULE MSP430;
  7. IMPORT SYSTEM;
  8. CONST
  9. iv = 0FFC0H;
  10. bsl = iv - 2;
  11. sp = bsl - 2;
  12. empty_proc = sp - 2;
  13. bits = empty_proc - 272;
  14. bits_offs = bits - 32;
  15. types = bits_offs - 2;
  16. int_offs = 0;
  17. trap_offs = 2;
  18. GIE* = {3};
  19. CPUOFF* = {4};
  20. OSCOFF* = {5};
  21. SCG0* = {6};
  22. SCG1* = {7};
  23. TYPE
  24. TInterrupt* = RECORD priority*: INTEGER; sr*: SET; pc*: INTEGER END;
  25. TTrapProc* = PROCEDURE (modNum, modName, err, line: INTEGER);
  26. TIntProc* = PROCEDURE (priority: INTEGER; interrupt: TInterrupt);
  27. PROCEDURE SetTrapProc* (TrapProc: TTrapProc);
  28. VAR
  29. ptr: INTEGER;
  30. BEGIN
  31. SYSTEM.GET(sp, ptr);
  32. IF TrapProc = NIL THEN
  33. SYSTEM.PUT(ptr + trap_offs, empty_proc)
  34. ELSE
  35. SYSTEM.PUT(ptr + trap_offs, TrapProc)
  36. END
  37. END SetTrapProc;
  38. PROCEDURE SetIntProc* (IntProc: TIntProc);
  39. VAR
  40. ptr: INTEGER;
  41. BEGIN
  42. SYSTEM.GET(sp, ptr);
  43. IF IntProc = NIL THEN
  44. SYSTEM.PUT(ptr + int_offs, empty_proc)
  45. ELSE
  46. SYSTEM.PUT(ptr + int_offs, IntProc)
  47. END
  48. END SetIntProc;
  49. PROCEDURE SetIntPC* (interrupt: TInterrupt; NewPC: INTEGER);
  50. BEGIN
  51. SYSTEM.PUT(SYSTEM.ADR(interrupt.pc), NewPC)
  52. END SetIntPC;
  53. PROCEDURE SetIntSR* (interrupt: TInterrupt; NewSR: SET);
  54. BEGIN
  55. SYSTEM.PUT(SYSTEM.ADR(interrupt.sr), NewSR)
  56. END SetIntSR;
  57. PROCEDURE [code] DInt*
  58. 0C232H; (* BIC #8, SR *)
  59. PROCEDURE [code] EInt*
  60. 0D232H; (* BIS #8, SR *)
  61. PROCEDURE [code] CpuOff*
  62. 0D032H, 16; (* BIS #16, SR *)
  63. PROCEDURE [code] Halt*
  64. 4032H, 0F0H; (* MOV CPUOFF+OSCOFF+SCG0+SCG1, SR *)
  65. PROCEDURE [code] Restart*
  66. 4302H, (* MOV #0, SR *)
  67. 4210H, 0FFFEH; (* MOV 0FFFEH(SR), PC *)
  68. PROCEDURE [code] SetSR* (bits: SET)
  69. 0D112H, 2; (* BIS 2(SP), SR *)
  70. PROCEDURE [code] ClrSR* (bits: SET)
  71. 0C112H, 2; (* BIC 2(SP), SR *)
  72. PROCEDURE [code] Delay* (n: INTEGER)
  73. 4035H, 124, (* MOV #124, R5 *)
  74. (* L2: *)
  75. 4114H, 2, (* MOV 2(SP), R4 *)
  76. 8324H, (* SUB #2, R4 *)
  77. (* L1: *)
  78. 4303H, (* NOP *)
  79. 4303H, (* NOP *)
  80. 4303H, (* NOP *)
  81. 4303H, (* NOP *)
  82. 4303H, (* NOP *)
  83. 8314H, (* SUB #1, R4 *)
  84. 3800H - 7, (* JGE L1 *)
  85. 4303H, (* NOP *)
  86. 8315H, (* SUB #1, R5 *)
  87. 3800H - 13; (* JGE L2 *)
  88. END MSP430.